Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-06-23
1997-04-29
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Bad bit
371 102, G11C 700
Patent
active
056255969
ABSTRACT:
A semiconductor memory device having a plurality of operating modes, and which offers improved operating speed without an increase in the chip surface area. The semiconductor memory device according to the present invention has access mode in which access is made in accordance with an external address signal, as well as at least one access mode in which access is performed of an internally generated address position, this semiconductor memory device further having a normal memory cell array, a redundancy memory cell array, a redundancy determining circuit which makes a determination of whether an address position to actually be accessed by a plurality of modes is an exchanged memory cell and which performs control so as to access that memory cell, a mode determining circuit which determines the mode, and an internal address generating circuit which internally and automatically generates an address position. In the semiconductor memory device configured this manner, at least part of the mode determination and the redundancy determination is performed in parallel.
REFERENCES:
patent: 4803656 (1989-02-01), Takemae
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 5097447 (1992-03-01), Ogawa et al.
patent: 5206831 (1993-04-01), Wakamatsu
Dinh Son T.
Fujitsu Limited
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