Semiconductor memory device with electrically rewritable and...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S185170, C365S185230, C365S185250, C365S189070

Reexamination Certificate

active

07453749

ABSTRACT:
A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.

REFERENCES:
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patent: 5740112 (1998-04-01), Tanaka et al.
patent: 6807096 (2004-10-01), Toda
patent: 6809989 (2004-10-01), Takahashi et al.
patent: 6847555 (2005-01-01), Toda
patent: 7064981 (2006-06-01), Roohparvar
patent: 2006/0239073 (2006-10-01), Toda
patent: 2007/0165473 (2007-07-01), Suzuki et al.
patent: 2008/0098165 (2008-04-01), Shinozaki et al.
U.S. Appl. No. 11/476,023, filed Jun. 28, 2006, Haruki Toda.
U.S. Appl. No. 11/832,987, filed Aug. 2, 2007, Toda.

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