Semiconductor memory device with data bus having plurality of I/

Details Semiconductor memory device with data bus having plurality of I/ Semiconductor memory device with data bus having plurality of I/

1995-09-22

1996-10-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518905, 365201, G11C 700

Patent

active

055638309

ABSTRACT:
The semiconductor memory device disclosed includes a data bus, an I/O terminal, a distributing circuit, a multiplexer circuit, and a latching circuit. The data bus includes a plurality of I/O pins. The distributing circuit divides the data bus into a first data bus and a second data bus constituted by data bus signal lines, and controls a state of connections of the data bus signal lines such that the state is either a one-to-one connection state or a one-to-many connection state with respect to predetermined I/O pins. The multiplexer circuit divides the data bus between the distributing circuit and the memory cell array into the second data bus and a third data bus constituted by data bus signal lines, and controls a state of connections of the data bus signal lines such that the state is either a one-to-one connection state or a many-to-one connection state. The latching circuit latches signals outputted from the second data bus and inputs signals as control signals into the multiplexer circuit. The testing operations respectively for a plurality of I/O pins can be carried out without being limited by the number of drivers/comparators.

REFERENCES:
patent: 5383157 (1995-01-01), Phelan
patent: 5416741 (1995-05-01), Ohsawa

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