Semiconductor memory device with burn-in test function

Details Semiconductor memory device with burn-in test function Semiconductor memory device with burn-in test function

2001-07-06

2002-06-04

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S225700

Reexamination Certificate

active

06400620

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-4586, filed on Jan. 31, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having a redundant circuit for replacing a defective cell with a redundant memory cell.
BACKGROUND OF THE INVENTION
Once semiconductor memory devices are produced, a screening operation is performed to detect and remove defective devices to ensure the overall quality of the devices. In one such screening operation, a bum-in test is executed, which can involve both field acceleration and temperature acceleration. In a bum-in test commonly called a stress test, the device is operated in a state wherein the voltage and temperature are set much higher than the normal operating voltage and temperature of the device. Moreover, a stress voltage higher than that which frequently causes initial failure during normal operation is applied to the device during a short time period. As a result, a device in which a defect may not otherwise exist until the device's initial operation is instead detected beforehand and removed from production. For the purpose of improving the production yield in accordance with increased capacitance and integration of the device, a redundancy scheme in which a redundant memory cell is used as a substitute for a defective cell is utilized. In the redundancy scheme, it is important to maximize redundancy flexibility in order to improve an efficiency of repair, minimizing increase in chip size.
To shorten the time used for the bum-in test operation, it is preferred to increase the time for applying high or low voltage to the entire cells through bit line sense amplifier, which is well known to those skilled in the art. In general, the burn-in test operation is carried out by selecting a number of array blocks more than the number of array blocks selected in the normal operation, activating word lines of the selected array blocks, and applying VCC or 0V to cells connected to the activated word lines.
FIG. 1
shows an example of the array blocks selected in the burn-in test operation in which the number of the array blocks is four times than that of the number of array blocks activated in the normal operation.
FIG. 2
shows another example that the number of the array blocks selected in the burn-in test operation is eight times than that of the number of array blocks in the normal operation.
If the number of the word lines being activated is increased to shorten the time for the burn-in test operation, a size of the array block where the word lines can be synchronously activated is accordingly decreased. As a result, row redundancy flexibility is decreased. Comparing the array blocks shown in
FIG. 2
with that of
FIG. 1
, the number of the word lines which can be synchronously activated is increased two times, whereby the size of the array blocks is decreased by half. At the same time, the row redundancy flexibility is decreased by half, defined within the size of the decreased blocks.
Consequently, according to the foregoing test scheme, the burn-in testing time can be reduced. However, it also decreases the redundancy flexibility, resulting in degrading the production yield. In order to improve the problems, it is desirable to increase the number of row redundancies, but the chip size is consequently increased.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of decreasing the time for burn-in test without decreasing row redundancy flexibility.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having a plurality of main cells and a plurality of redundant cells. The device includes an address storage and decoding circuit, and a master fuse circuit. The address storage and decoding circuit stores address information to assign a defective main cell of the main cells, and generates a redundant flag signal when the defective main cell corresponding to the stored address information is assigned by a current address information. The master fuse circuit generates switch control signals in accordance with a connected state of the master fuse storing whether the defective main cell is replaced with the redundant cell. During a burn-in test mode for the main cells, the master fuse circuit generates the switch control signals in response to a burn-in test signal. The switch control signals shut the address information off not to be provided to the address storage and decoding circuit regardless of the connected state of the master fuse.
In the semiconductor memory device according to the present invention, a redundant word line is not assigned when the burn-in test operation is carried out.
According to the semiconductor memory device of the present invention, the time for the burn-in test operation can be reduced by making a lot of word lines synchronously activated in order to give stress on many cells during the burn-in test operation. Further, the production yield can be improved by maximizing row redundancy flexibility to minimize an increase of chip size during the normal operation.
As a result, it is possible to reduce the burn-in test time by maximizing the efficiency of row redundancy, with maximizing the number of the word lines being synchronously activated in the burn-in test operation.


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patent: 5748543 (1998-05-01), Lee et al.
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patent: 6067268 (2000-05-01), Lee
patent: 6094382 (2000-07-01), Choi et al.
patent: 6272056 (2001-08-01), Ooishi

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