Semiconductor memory device with bit line sense amplifiers

Details Semiconductor memory device with bit line sense amplifiers Semiconductor memory device with bit line sense amplifiers

1987-02-26

1988-12-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365149, 365210, G11C 700

Patent

active

047929278

ABSTRACT:
In a dynamic random access memory with a folded bit line structure, in which a memory cell array is divided into a plurality of blocks (CAL1, CAL2) and the bit lines (BL1, BL1, BL2, BL2) of the adjacent blocks (CAL1, CAL2) are connected to each other by using transfer gate transistors (QT1, QT2), sense amplifiers (SA1, SA2) and restore circuits (RE1, RE2) for detecting potential difference between pair of bit lines are provided for each of the pairs of bit lines (BL1, BL1, BL2, BL2) of each of the blocks (CAL1, CAL2), the transfer gate transistors (QT1, QT2) to turned on by being triggered by an activating signal to a restore circuit first operated, out of restore circuits connected to bit lines connected to the transfer gate transistor (QT1, QT2).

REFERENCES:
patent: 4584672 (1986-04-01), Schutz et al.
patent: 4598387 (1986-07-01), Chwang et al.
patent: 4651306 (1987-03-01), Yanagisawa
Digest of Technical Papers, ISSCC, 1984, pp. 278-279, Roger I. Kung et al. "A Sub 100ns 256K DRAM in CMOS III Technology."

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