Semiconductor memory device with a stacked capacitor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257305, 257306, H01L 2968

Patent

active

052084701

ABSTRACT:
The semiconductor memory device with a stacked capacitor is disclosed. When the mis-align is generated in forming contact region 42 for contact between the storage electrode of the stacked capacitor and the source region 34, the ion-implantation process, with the same conductive type as that of the source region, is carried out, to form the another source region 48 under the bottom surface of the contact region 42, wherein the polysilicon layer on the substrate is used as the mask. The successive ion-implantation provides the diffusion region 58 capable of wholly surrounding the another source region 48, wherein the diffusion region 58 contains higher concentration than that of the substrate and simultaneously lower than that of the source region, with the same conductive type as that of substrate. On the other hand, when no mis-align is generated, the semiconductor memory device further comprises another diffusion region 58a formed below the source region 34a, the diffusion region 58a having the opposite conductive type to that of the source region. Thereby the memory device is provided with the improvement of the refresh characteristic and with decrease of the soft error rate.

REFERENCES:
patent: 4994889 (1991-02-01), Takeuchi et al.
patent: 5017982 (1991-05-01), Kobayashi
patent: 5068707 (1991-11-01), Pors et al.

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