Semiconductor memory device with a controlled precharging arrang

Details Semiconductor memory device with a controlled precharging arrang Semiconductor memory device with a controlled precharging arrang

1984-08-08

1987-02-17

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365203, 365181, G11C 1300

Patent

active

046445005

ABSTRACT:
A semiconductor memory device includes: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to or from the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; a first conductive type MOSFET with a source thereof being connected to a power supply terminal, with a gate thereof being connected to the writing-in control signal line, and with a drain thereof being connected to the bit line; the first conductive type MOSFET being adapted to charge up the bit line when no writing is performed in the memory cell; a second conductive type MOSFET with first control line thereof being connected to the bit line, with a gate thereof being connected to the writing-in control signal line, and with a second control line thereof being connected to the output terminal of the writing circuit; and the second conductive type MOSFET being adapted to transmit to the bit line an output from the writing circuit.

REFERENCES:
patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4417328 (1983-11-01), Ochii
Schlageter et al, "A 4K Static 5-V RAM", 1976 IEEE International Solid-State Circuits Conference, pp. 136-137, Feb. 19, 1976.

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