Semiconductor memory device using cross-coupled load and prechar

Details Semiconductor memory device using cross-coupled load and prechar Semiconductor memory device using cross-coupled load and prechar

1997-12-16

1999-01-26

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

365156, 365154, 365177, 365202, 36518911, 36518909, G11C 700

Patent

active

058645110

ABSTRACT:
Bit lines (BL, /BL) are equally held low by a low-level precharge circuit (212) and an equalizing circuit (218) at time (t1) prior to a read operation. A read signal (/READ) and an equalization signal (EQ) go low at time (t2) when the read operation starts to provide "H" to word lines (WLU, WLL). If storage nodes (N1, N2) store "H" and "L" respectively, a bipolar transistor (BP2) is activated when the bit line (/BL) reaches a potential (+Vbe). Then, the potential of the bit line (/BL) does not rise to a power supply potential (VCC) but is held at the potential (+Vbe). Current flows to the bit line (/BL) through a reading load circuit (211) transiently (for a time period between times t2 and t3), but no current flows to the bit line (/BL) in a steady state (for a time period between times t3 and t4).

REFERENCES:
patent: 4868628 (1989-09-01), Simmons
patent: 5483483 (1996-01-01), Choi et al.
patent: 5754487 (1998-05-01), Kim et al.
patent: 5764565 (1998-06-01), Sato et al.

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