Semiconductor memory device to reduce parasitic output capacitan

Details Semiconductor memory device to reduce parasitic output capacitan Semiconductor memory device to reduce parasitic output capacitan

1977-03-15

1978-09-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, G11C 706

Patent

active

041141920

ABSTRACT:
A semiconductor memory device includes a memory circuit formed of a plurality of matrix-arranged memory cells, a plurality of output data lines, each of which is connected to memory cells arranged in the same column of the matrix memory circuit, and a plurality of data-sensing circuits for delivering output data from the matrix memory circuit to an output device. The data-sensing circuits are divided into a plurality of groups, and the semiconductor memory device further comprises clocked inverters whose input terminals are connected to the output terminals of the respective groups of sensing circuits and whose output terminals are connected to the output device, and a control circuit which, when one of the data-sensing circuits issues an output, supplies an energizing signal to that of the clocked inverters which is connected to said one data-sensing circuit.

REFERENCES:
patent: 3665426 (1972-05-01), Gross et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4040015 (1976-06-01), Fukuda
Curtis, Complementary Metal-Oxide Semiconductor Logic Testability, IBM Technical Disclosure Bulletin, vol. 16, No. 2, 7/73, pp. 404-405.
Scarpero, Field-Effect Transistor Bidirectional Driver Control Circuit, IBM Technical Disclosure Bulletin, vol. 16, No. 8, 1/74, pp. 2442-2443.

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