Semiconductor memory device that can carry out read disturb test

Details Semiconductor memory device that can carry out read disturb test Semiconductor memory device that can carry out read disturb test

1997-11-26

1999-06-29

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

36518911, G11C 700

Patent

active

059177667

ABSTRACT:
A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connected to the boosted voltage supply line. In a disturb accelerated test mode or in a burn-in test mode, an external voltage is supplied from an external power supply to the input terminal. A word line is reliably boosted in voltage in a disturb accelerated test mode.

REFERENCES:
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5388077 (1995-02-01), Sanada
patent: 5424990 (1995-06-01), Ohsawa
patent: 5504715 (1996-04-01), Lee et al.
patent: 5568436 (1996-10-01), Furuyama

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