Semiconductor memory device testable with a single data rate...

Details Semiconductor memory device testable with a single data rate... Semiconductor memory device testable with a single data rate...

2003-12-30

2008-11-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07454672

ABSTRACT:
Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

REFERENCES:
patent: 5008886 (1991-04-01), Chinnaswamy et al.
patent: 6317372 (2001-11-01), Hayashi et al.
patent: 6516363 (2003-02-01), Porter et al.
patent: 2000-207900 (2000-07-01), None
patent: 10-2000-0062531 (2000-10-01), None

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