Semiconductor memory device, system and method of testing same

Details Semiconductor memory device, system and method of testing same Semiconductor memory device, system and method of testing same

2007-01-05

2008-11-25

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S194000, C365S189050, C365S230080

Reexamination Certificate

active

07457179

ABSTRACT:
A semiconductor memory device includes a plurality of address pads, a plurality of DQ pads, an address buffer, a data input buffer, a latch circuit and a first delay circuit. The address buffer receives a plurality of first address signals through the address pads and buffers the first address signals to generate a plurality of second address signals. The data input buffer receives one of a plurality of input data through the DQ pads and buffers the input data to generate a first data or receives the first address signals through the DQ pads and buffers the address signals to generate a plurality of third address signals. The latch circuit latches the third address signals to generate fourth address signals in response to a test mode control signal. The first delay circuit selects the second address signals or the fourth address signals and delays the selected address signals for a predetermined time to generate fifth address signals.

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patent: 11-306796 (1999-11-01), None
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