Semiconductor memory device supporting two data ports

Details Semiconductor memory device supporting two data ports Semiconductor memory device supporting two data ports

2005-04-26

2005-04-26

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

06885609

ABSTRACT:
A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the transistors, two PMOS transistors and six NMOS transistors are disposed in one N-well area and one contiguous P-well area of a semiconductor substrate, respectively. The N-well area is disposed at a corner of the memory cell for improving efficiency of the layout. Since one N-well area and one P-well area are formed in the semiconductor substrate, the size of an isolated area between the N-well area and the P-well area can be reduced, thus also reducing the size of a memory cell.

REFERENCES:
patent: 5754468 (1998-05-01), Hobson
patent: 6341083 (2002-01-01), Wong
patent: 6347062 (2002-02-01), Nii et al.
patent: 6590802 (2003-07-01), Nii
patent: 10-178110 (1999-07-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device supporting two data ports does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device supporting two data ports, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device supporting two data ports will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3411202