Semiconductor memory device storing two types of binary number d

Static information storage and retrieval – Read/write circuit – Multiplexing

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36518908, 36523002, G11C 700

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active

053233476

ABSTRACT:
A semiconductor memory device 1 includes a plurality of memory circuits 10. Each of the memory circuits 10 includes a data bit memory cell 11, a sign bit memory cell 12, a converting circuit 13 and a selecting circuit 14. The data bit memory cell 11 stores one bit of binary number data or a data bit of redundant binary number data. The sign bit memory cell 12 stores a digit of a sign bit of redundant binary number data. The converting circuit 13 converts redundant binary number data into binary number data on the basis of the data bit stored in the data bit memory cell and the sign bit stored in the sign bit memory cell 12. The selecting circuit 14 selects the data bit stored in data bit memory cell 11 or the one bit of binary number data outputted by the converting circuit 13.

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patent: 5150321 (1992-09-01), Keating
"A VLSI-Oriented High-Speed Multiplier Using a Redundant Binary Addition Tree", by Naofumi Takagi et al, Institute of Electronics and Communication Engineers of Japan, Jun. 1983 vol. J66-D No. 6, pp. 683-690.
"A 200MHz16-bit BiCMOS Signal Processor", Masakazu Yamashina et al, ISSCC 89 Digest of Technical Papers, Feb. 1989, pp. 172-173.
"A 33MFLOPS Floating Point Processor Using Redundant Binary Representation", by Hisakazu Edamatsu, 1988 ISSCC Digest of Technical Papers, Feb. 1988 pp. 152-153.

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