Semiconductor memory device providing external output data signa

Details Semiconductor memory device providing external output data signa Semiconductor memory device providing external output data signa

1994-09-12

1996-01-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365205, 365207, 365208, G11C 700

Patent

active

054814979

ABSTRACT:
Read data supplied from one of a plurality of differential amplifier circuits is transmitted to a read data bus driver circuit via one of a plurality of CMOS transfer gates and a data latch circuit. The potential of read data bus pair is forcedly set to a low level in response to a control signal until the read data is transmitted to the read data bus driver circuit. Thereafter, the read data bus driver circuit drives the read data bus pair in accordance with the transmitted read data. Thereby, a speed of the address access operation can be increased without outputting invalid data.

REFERENCES:
patent: 5088065 (1992-02-01), Hanamura
patent: 5146427 (1992-09-01), Sasaki
patent: 5233558 (1993-08-01), Fujii
patent: 5311471 (1994-05-01), Matsumoto
"A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", WADA et al., IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 727-732.
"A 33-ns 64-Mb DRAM", Oowaki et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1498-1505.

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