Semiconductor memory device of double-data rate mode

Details Semiconductor memory device of double-data rate mode Semiconductor memory device of double-data rate mode

1999-03-16

2000-11-28

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

36518905, 365233, G11C 700

Patent

active

061543934

ABSTRACT:
Two data items are simultaneously read from memory cells and are fetched into a bus exchanger. The bus exchanger selects the connection between the memory cells and a first output register and the connection between the memory cells and a second output register, in accordance with prescribed rules. The two data items are output to the first and second output registers, respectively. The first output register comprises a master latch. The second output register comprises a master latch and a slave latch. A multiplexer outputs, as output signals, the data items stored in the first and second output registers. The transistors constituting the second output register have smaller sizes (channel widths) than the transistors constituting the first output register. Since the first output register comprises one master latch only, it is possible to reduce the gate capacitance of the loads driven by the clock signal for controlling both output registers.

REFERENCES:
patent: 5530955 (1996-06-01), Kaneko
patent: 5748561 (1998-05-01), Hotta
patent: 5757704 (1998-05-01), Hachiya
patent: 6031410 (2000-02-01), Kanno
Cheryl L. Stout Et Al., "10 Gb/s Silicon Bipolar 8:1 Multiplexer and 1:8 Demultiplexer", IEEE Journal of Solid State Circuits, vol, 28, No. 3, Mar. 1993, pp. 339-343.

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