Semiconductor memory device of bit line twist system

Details Semiconductor memory device of bit line twist system Semiconductor memory device of bit line twist system

2006-04-25

2006-04-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C714S048000

Reexamination Certificate

active

07035153

ABSTRACT:
A semiconductor memory device adopting a bit line twist system in which at least a part of bit lines are twisted, includes memory cell arrays each having a plurality of memory cells to store data, redundancy cell arrays each having a plurality of redundancy cells to replace a defective cell in the memory cell array, and a control circuit which performs control to invert a direction of the data. The device further includes an inversion circuit which inverts the direction of the data, in accordance with the control by the control circuit.

REFERENCES:
patent: 2001/0046166 (2001-11-01), Fischer et al.
patent: 2003/0002361 (2003-01-01), Fischer et al.
patent: 62-51096 (1987-03-01), None
patent: 6-314498 (1994-11-01), None

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