Semiconductor memory device, memory system having...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C711S154000

Reexamination Certificate

active

07634697

ABSTRACT:
Embodiments of the invention include features in the semiconductor memory device that are configured to receive command signals from a memory controller and selectively output at least a portion of the received command signals back to the memory controller for verification. Embodiments of the invention also provide methods for verifying the proper communication of command signals from a memory controller to a semiconductor memory device. Embodiments of the invention also provide systems and methods for testing memory cells in a semiconductor memory device.

REFERENCES:
patent: 2003/0095455 (2003-05-01), Dono et al.
patent: 2007/0180202 (2007-08-01), Kawabata et al.
patent: 2009/0063916 (2009-03-01), Vogelsang
patent: 06052694 (1994-02-01), None
patent: 2003256232 (2003-09-01), None
patent: 2005107599 (2005-04-01), None
patent: 1020040020807 (2004-03-01), None
patent: 1020040095892 (2004-11-01), None
patent: 1020060073045 (2006-06-01), None

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