Semiconductor memory device including programmable output...

Details Semiconductor memory device including programmable output... Semiconductor memory device including programmable output...

2000-03-31

2001-06-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S201000

Reexamination Certificate

active

06252805

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-16008, filed on May 4, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to the testing of semiconductor memory devices having memory modules.
High speed semiconductor memory devices are partially designed to receive or transmit input and output signals such as data or addresses through a bus-type transmission line. In the bus-type structure, various semiconductor memory devices are connected in common to one bus, and only one semiconductor memory device can load data onto the bus at the time. If two or more semiconductor memory devices simultaneously attempt to load data onto the bus, the data collides with each other, which causes a malfunction.
A Rambus dynamic random access memory (DRAM), which is a type of high speed semiconductor memory device, employs the above-described bus-type structure, as well as a proposed special module for supporting the bus-type structure.
FIG. 1
is a block diagram of a Rambus DRAM memory module having the bus-type structure.
Referring to
FIG. 1
, a memory module
200
includes a plurality of semiconductor memory devices M
1
through M
n
, each having a plurality of input and output pins DQ
1
to DQ
w,
i.e., Rambus DRAMs. Furthermore, identical input and output pins of the semiconductor memory devices M
1
to M
n
are connected in common to a corresponding data bus. In other words, first input and output pins DQ
1
of each of the semiconductor memory devices M
1
to M
n
are connected in common to a data bus DB
1
; second input and output pins DQ
2
are connected in common to a data bus DB
2
; and so on until W
th
input and output pins DQ
w
of the semiconductor memory devices M
1
to M
n
are connected in common to a w
th
data bus DB
w
. Input and output pins of a controller
100
, which is a master controller, are connected to corresponding data buses.
In the memory module having the bus-type structure of
FIG. 1
, identical data can be simultaneously written to various semiconductor memory devices during a write operation. However, when data is simultaneously read from two or more semiconductor memory devices during a read operation, the data collides with each other on the data bus. As a result, data may only be read from one semiconductor memory devices at a time.
FIG. 2
is a block diagram of a conventional output data merge circuit which is in each of the semiconductor memory devices of FIG.
1
. Referring to
FIG. 2
, during a normal mode, a plurality of output data DO
1
to DO
w
read from a memory cell array
21
are simultaneously output through a plurality of output pins DQ
1
through DQ
w
. During a test mode, however, a comparator
22
merges the plurality of output data DO
1
through DO
w
read from the memory cell array
21
and outputs the result to a single predetermined output pin, e.g., DQ
1
.
Thus, when the semiconductor memory devices, including the output data merge circuit of
FIG. 2
, are employed as the memory modules of
FIG. 1
, all of the semiconductor memory devices output their data to a data bus, e.g., a data bus DB
1
through a predetermined output pin DQ
1
during read operations of a test mode. Thus, when the data is read from two or more semiconductor memory devices, the data collide with each other on the data bus DB
1
.
As a result, when the semiconductor memory devices, including the conventional output data merge circuit, are employed in the memory module of
FIG. 1
, the data must be read from only one semiconductor memory device at a time during testing of the memory module. In other words, only one semiconductor memory device can be tested at a time, so that memory module time is lengthened.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a semiconductor memory device capable of programmably varying a pin that transmits output data during a test mode to read data simultaneously from various semiconductor memory devices during the testing of a memory module having the bus-type structure described above.
It is another objective of the present invention to provide a read method in a test mode of a semiconductor memory device capable of simultaneously reading data from various semiconductor memory devices during the testing of the memory module having the bus-type structure described above.
It is still another objective of the present invention to provide a method for testing a memory module capable of reducing test time of the memory module having the bus-type structure described above.
Accordingly, to achieve the first objective, there is provided a semiconductor memory device, comprising a memory cell array providing a plurality of output data, a plurality of output pins connected to the memory cell array, a comparator that compares the plurality of output data, and provides a comparison result signal, and an output pin determining unit that programmably selects one of the plurality of output pins. During a test mode, the comparison result signal is output through the selected output pin.
Only the comparison result signal is transmitted through the selected output pin during the test mode. The plurality of output data are output through the plurality of output pins during a normal mode.
The comparator may comprise an exclusive or gate. The output pin determining unit may comprise a register that stores a predetermined number applied from the outside of the semiconductor memory device, and a selection unit that selects one of the plurality of output pins based on the predetermined number. The selection unit may itself further comprise a demultiplexer for providing the comparison result signal only to the selected output pin.
The semiconductor memory device may further comprise a plurality of multiplexers, each connected to one of the plurality of output pins, for connecting the memory cell array to the plurality of output pins during a normal operation mode, and for connecting the comparison result signal to the selected output pin during the test mode. The output pin determining unit and the plurality of multiplexers are all preferably controlled by a test control signal.
To achieve the second objective, there is provided a read method of a test mode with respect to a semiconductor memory device including a memory cell array and a plurality of output pins. The method comprises storing a predetermined number applied from the outside of the semiconductor memory device, selecting one of the plurality of output pins corresponding to the predetermined number, comparing a plurality of output data read from the memory cell array during the test mode to generate a comparison result signal, and outputting the comparison result signal to the selected output pin.
To achieve the third objective, there is provided a method for testing a memory module that comprises a plurality of semiconductor memory devices having a memory cell array and a plurality of output pins, the semiconductor memory devices being connected in common to a plurality of data buses corresponding to output pins of the semiconductor memory device. The method comprises applying one of a plurality of predetermined numbers to each of the semiconductor memory devices to determine a corresponding output pin for each of memory devices during a test mode, and reading data synchronously from each of the semiconductor memory devices via output pins corresponding to the predetermined numbers applied to each memory device. If possible, the predetermined numbers should all be mutually exclusive.


REFERENCES:
patent: 5757809 (1998-05-01), Kiso et al.

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