Semiconductor memory device including main/sub-bit line arrangem

Details Semiconductor memory device including main/sub-bit line arrangem Semiconductor memory device including main/sub-bit line arrangem

1996-09-13

1998-03-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365205, 36523003, G11C 700

Patent

active

057320268

ABSTRACT:
A semiconductor memory device including a plurality of sub-bit lines, a sense amplifier provided in common to the plurality of sub-bit lines which receives a data signal from a first one of the plurality of sub-bit lines, a main-bit line operatively coupled to the sense amplifier to receive an output of the sense amplifier, and a data latch circuit provided to latch data appearing on the main-bit line. The device further comprises a circuit for transferring a data signal of a second one of the plurality of sub-bit lines to the sense amplifier when the data latch circuit is being accessed to read out data latched in the data latch circuit.

REFERENCES:
patent: 5274598 (1993-12-01), Fujii et al.
patent: 5353255 (1994-10-01), Komuro

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