Semiconductor memory device including 4TSRAMs

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S156000, C365S230060, C257S135000

Reexamination Certificate

active

10878050

ABSTRACT:
Disclosed is a method of improving stability of a memory cell in read mode in an SRAM including a memory cell comprising two access MOS transistors and two drive MOS transistors. The magnitude of voltage between gate and source of an access transistor of a memory cell connected to a selected word line is controlled to be smaller than a power-supply voltage by controlling the voltage of selected word line WL in read mode.

REFERENCES:
patent: 4751683 (1988-06-01), Wada et al.
patent: 6212124 (2001-04-01), Noda
patent: 6259623 (2001-07-01), Takahashi
patent: 6344992 (2002-02-01), Nakamura
patent: 6608780 (2003-08-01), Shau
patent: 2002/0051379 (2002-05-01), Deng et al.
patent: 2003/0007380 (2003-01-01), Houston
patent: 2003/0032250 (2003-02-01), Imai
patent: 2004/0100816 (2004-05-01), Forbes
patent: 2003-133441 (2003-05-01), None

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