Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-06
2007-02-06
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S305000
Reexamination Certificate
active
10949447
ABSTRACT:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a portion of the cap poly layer from the PMOS region. Subsequently, the same resist mask and/or remaining portion of the cap poly layer is employed to form source/drain regions within the PMOS region by implanting a p-type dopant. Afterward, a cap poly thermal process is performed that causes tensile strain to be induced only in channel regions of devices located within the NMOS region. As a result, channel mobility and/or performance of devices located in the PMOS region is not substantially degraded.
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Antonio L. P. Rotondaro, et al., “Method to Selectively Recess Etch Regions on a Wafer Surface Using Capoly as a Mask” U.S. Appl. No. 10/931,195, filed Aug. 31, 2004.
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Pacheco Rotondaro Antonio Luis
Sridhar Seetharaman
Brady W. James
Keagy Rose Alyssa
Thomas Toniae M.
Wilczewski M.
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