Semiconductor memory device having zigzag bonding pad arrangemen

Details Semiconductor memory device having zigzag bonding pad arrangemen Semiconductor memory device having zigzag bonding pad arrangemen

1996-03-19

1998-12-29

Arroyo, Teresa Maria

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257666, 257908, 257784, H01L 2348

Patent

active

058545085

ABSTRACT:
Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

REFERENCES:
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 5068712 (1991-11-01), Murakami et al.
patent: 5196910 (1993-03-01), Moriuchi et al.
patent: 5331201 (1994-07-01), Nishino
patent: 5579256 (1996-11-01), Kajigaya et al.

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