Semiconductor memory device having wafer burn-in test mode

Details Semiconductor memory device having wafer burn-in test mode Semiconductor memory device having wafer burn-in test mode

2007-12-28

2010-02-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

Reexamination Certificate

active

07660174

ABSTRACT:
A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals.

REFERENCES:
patent: 5638331 (1997-06-01), Cha et al.
patent: 6259638 (2001-07-01), Kim
patent: 6414890 (2002-07-01), Arimoto et al.
patent: 6996753 (2006-02-01), Cho
patent: 10-0182973 (1998-12-01), None
patent: 10-0259336 (2000-03-01), None
patent: 10-2003-0051030 (2003-06-01), None
patent: 10-2007-0036600 (2007-04-01), None

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