Semiconductor memory device having two column transfer gate tran

Details Semiconductor memory device having two column transfer gate tran Semiconductor memory device having two column transfer gate tran

1989-05-12

1990-02-13

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365182, G11C 700, G11C 1140

Patent

active

049012819

ABSTRACT:
A semiconductor memory device, including a plurality of programmable read only memory cells arranged at intersection points of a matrix formed by a plurality of word-lines and bit-lines crossing each other, independently having first column transfer gate transistors located between a programming circuit and the bit-lines to transfer a programming data signal from the programming circuit to a selected memory cell located on one of the bit-lines when the memory device is in a programming mode and second column transfer gate transistors located between a sense amplifier and the bit-lines to transfer a read out data signal from a selected memory cell located on one of the bit-lines to a sensing amplifier when the memory device is in a reading mode.

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