Static information storage and retrieval – Read/write circuit – Precharge
Patent
1990-12-26
1992-08-11
Sniezek, Andrew L.
Static information storage and retrieval
Read/write circuit
Precharge
365210, 365208, 36518909, G11C 700
Patent
active
051385791
ABSTRACT:
A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4475178 (1984-10-01), Kinoshita
patent: 4694427 (1987-09-01), Miyamoto et al.
patent: 4730279 (1988-03-01), Ohtani
patent: 4792928 (1988-12-01), Tobita
patent: 4884241 (1989-11-01), Tanaka et al.
William Ip, Te-Long Chiu, Tsung-Ching Wu, Gust Perlegos, 1984 ISSCC Digest of Technical Papers, IEEE p. 138 (Feb. 23, 1984).
Jeffrey M. Schlageter, et al; 1976 ISSCC, Digest of Technical Papers, IEEE p. 136 (Feb. 19, 1976).
Asano Masamichi
Imai Mizuho
Iwahashi Hiroshi
Minagawa Hidenobu
Tatsumi Yuuichi
Kabushiki Kaisha Toshiba
Sniezek Andrew L.
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