Semiconductor memory device having self-refresh and back-bias ci

Details Semiconductor memory device having self-refresh and back-bias ci Semiconductor memory device having self-refresh and back-bias ci

1992-11-25

1994-05-24

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

36518909, 365227, 365228, 365236, 3652257, 3072962, 3072965, G11C 11402, G11C 702

Patent

active

053155572

ABSTRACT:
A semiconductor memory device includes a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies and a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors. A back-bias generator having an oscillator and a back-bias voltage detecting circuit and a selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal. The oscillator output, together with the output of the back-bias control pulse generator, cause a driver control circuit to feed a drive signal to a charge pump during a self-refresh operation.

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Konishi et al., "A 38-ns 4-Mb DRAM with a Battery-Backup (BBU) Mode", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct., 1990, pp. 1112-1117.

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