Semiconductor memory device having self-aligned contacts and...

Details Semiconductor memory device having self-aligned contacts and... Semiconductor memory device having self-aligned contacts and...

2005-04-26

2005-04-26

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000

Reexamination Certificate

active

06885052

ABSTRACT:
A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

REFERENCES:
patent: 6074918 (2000-06-01), Lee
patent: 6150213 (2000-11-01), Luo et al.
patent: 6177307 (2001-01-01), Tu et al.
patent: 6255160 (2001-07-01), Huang
patent: 6348375 (2002-02-01), Lee et al.
patent: 6437411 (2002-08-01), Choi et al.
patent: P1997-003953 (1995-06-01), None
patent: P2000-0015299 (1998-08-01), None

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