Semiconductor memory device having select circuit

Details Semiconductor memory device having select circuit Semiconductor memory device having select circuit

2002-10-09

2004-10-19

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S190000

Reexamination Certificate

active

06807108

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to a semiconductor memory device which receives data from an external data bus.
2. Description of the Background Art
FIG. 29
is a block diagram showing the configuration of a data processing system which employs a plurality of semiconductor memory devices.
Referring to
FIG. 29
, a data processing system
200
includes a controller
201
, a PLL circuit
202
and a plurality of semiconductor memory devices
203
.
Controller
201
controls overall processing system
200
. Controller
201
outputs an address signal ADD for designating each semiconductor memory device
203
and a data signal DQ for transmitting data to each semiconductor memory device
203
, to a plurality of semiconductor memory devices
203
. In addition, controller
201
outputs a clock signal CLK to PLL circuit
202
.
PLL circuit
202
consists of a buffer circuit. PLL circuit
202
receives the signal outputted from controller
201
and outputs a clock signal EXTCLK for controlling respective semiconductor memory devices
203
. It is noted that a clock signal bus
204
is grounded for each semiconductor memory device
203
.
Each semiconductor memory device
203
converts data signal DQ transmitted from controller
201
into an internal data signal DIN by an input buffer grounded in each memory
203
.
FIG. 30
is a circuit diagram showing the configuration of the input buffer grounded in each memory
203
shown in FIG.
29
.
Referring to
FIG. 30
, input buffer
100
includes P-channel MOS transistors
1
to
4
and N-channel MOS transistors
5
to
8
.
P-channel MOS transistors
1
and
2
, and N-channel MOS transistors
5
,
6
and
8
constitute a comparator. P-channel MOS transistors
1
and
2
constitute a current mirror circuit and the sources thereof are connected to an internal power supply potential node
9
.
The source of N-channel MOS transistor
8
is connected to a ground potential node
10
and a control signal EN generated inside semiconductor memory device
203
is inputted into the gate of N-channel MOS transistor
8
. Control signal EN is a signal the level of which becomes H level when input buffer
100
operates.
An external data signal EXTDQ transmitted from controller
201
is inputted into the gate of N-channel MOS transistor
5
. In addition, a reference potential VREF is inputted into the gate of N-channel MOS transistor
6
. Reference potential VREF is generated inside of semiconductor memory device
203
. The sources of both N-channel MOS transistors
5
and
6
are connected to the drain of N-channel MOS transistor
8
.
Each of MOS transistors
1
,
2
,
5
,
6
and
8
compares the level of external data signal EXTDQ with that of reference potential VREF and outputs a signal VO at potential level according to the comparison result.
P-channel MOS transistor
4
and N-channel MOS transistor
7
constitute an inverter
11
. Inverter
11
receives and inverts signal VO and outputs the inverted signal as internal data signal DIN.
The source of P-channel MOS transistor
3
is connected to the sources of P-channel MOS transistors
2
and
4
and the drain thereof is connected to the drain of P-channel MOS transistor
2
and the gate of P-channel MOS transistor
4
. Control signal EN is inputted into the gate of P-channel MOS transistor
3
. As a result, when control signal EN is at H level, input buffer
100
stops operating.
Acceleration and low power consumption have been recently demanded for the data processing system which employs the semiconductor memory devices respectively including the input buffers constituted as described above. To meet the demand, therefore, the data processing system has been accelerated year by year. However, following the acceleration, noise which is generated on a transmission path has become disadvantageous to the data processing system.
In the data processing system, various external factors are applied to thereby increase power supply noise on a substrate. In addition, the data processing system has a disadvantage in that DQ coupling noise is generated depending on the wiring layout of transmission paths which connect the controller to the semiconductor memory devices in the data processing system. In designing the transmission paths of the data processing system, therefore, it is necessary to consider the improvement of noise resistance.
A circuit configuration which enables the improvement of the noise resistance is reported in Japanese Patent Laying-Open No. 3-171849.
FIG. 31
is a circuit diagram showing the configuration of an input buffer which enables the improvement of noise resistance.
Referring to
FIG. 31
, input buffer
101
, similar to input buffer
100
, includes P-channel MOS transistors
1
to
4
and N-channel MOS transistors
5
to
8
.
An external data signal ZEXTDQ instead of reference potential VREF is inputted into the gate of N-channel MOS transistor
6
of input buffer
101
, compared with input buffer
100
. External data signal ZEXTDQ is a complementary signal to external data signal EXTDQ. Since the remaining circuit configuration is the same as that of input buffer
100
, it will not be repeatedly described herein.
Semiconductor memory device
203
including input buffer
101
shown in
FIG. 31
receives complementary external data signals EXTDQ and ZEXTDQ from controller
201
. Therefore, controller
201
is connected to respective semiconductor memory devices
203
by complementary data buses.
According to the above-mentioned configuration, each semiconductor memory device
203
is connected to the complementary data buses and complementary external data EXTDQ and ZEXTDQ are transmitted on the complementary data buses. As a result, coupling noise generated on the data buses turns into a common mode. Therefore, the common mode noise transmitted by the complementary data buses can be offset each other by the amplification operation of the comparator in input buffer
101
.
As described above, if the input buffer is constituted to input complementary external data signals into the input buffer, it is possible to decrease the amplitude of each signal transmitted on the data bus. In addition, compared with input buffer
100
which receives reference potential VREF, input buffer
101
has improved through rate dependency and VCC dependency.
Consequently, by constituting the complementary data buses, it is possible to decrease the power consumption of the data processing system.
As described above, if the data processing system has, as the transmission paths, the complementary data buses which transmit complementary signals, the noise resistance of the system is improved, whereby the data processing system can operate stably.
However, if wirings as many as those used in double data buses transmitting complementary signals are used in a single data bus, data twice as many can be transferred to the complementary buses. Therefore, despite a disadvantage in the stability of the operation more or less, the usage range of such a data processing system is sufficiently wide.
Further, since various types of data processing systems are present, it is more preferable that the degree of freedom for transmission path design is increased so as to be able to correspond to various types of systems.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of corresponding to various types of data processing systems.
A semiconductor memory device according to the present invention includes an input buffer and a select circuit. The input buffer receives a first data signal inputted from an outside of the semiconductor memory device, a second data signal complementary to the first data signal and inputted from the outside, and a reference signal, and generates an internal data signal. The select circuit selects a signal used when the input buffer generates the internal data signal, from the second data signal and the reference signal.
It is thereby pos

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