Semiconductor memory device having row buffers

Details Semiconductor memory device having row buffers Semiconductor memory device having row buffers

2001-10-30

2003-10-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230080, C365S233100, C365S236000, C365S239000, C365S194000, C365S189120

Reexamination Certificate

active

06636443

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having row buffers capable of transmitting cell array data from DRAM including the row buffer to the external by one command.
2. Description of the Related Art
Generally, performance of computer system is lowered by performance difference between processors and memory. This is because efforts are focused on improving operation speed of processors and increasing capacity of memory. Therefore, in order to overcome the degradation, researches are being developed on methods for increasing operation bandwidth of memory or rapidly generating column address which is successively generated when a row is enabled.
However, it is difficult to increase effective bandwidth since recent computer systems have irregular memory access pattern in a memory area. Accordingly, researches are also being developed on a method for shortening latency of row cycle in order to improve effective bandwidth. For example, row buffers (in other words, register) have been formed in DRAM according to a conventional method. And, when accessed data are stored in the row buffer, the data are outputted without accessing data of memory cell. Therefore, row cycle is shortened and effective bandwidth is improved.
In another method such as cache DRAM, DRAM and SRAM are included in one chip to use SRAM as row buffer or to access DRAM and SRAM respectively. However, there is a problem in compatibility with DRAM. Therefore, only row buffers are used in order to interface with the external. Generally, DRAMs use background operation and foreground operation in order to read data stored in the row buffer (register). The background operation is performed between the inner part of DRAM and row buffer and the foreground operation between row buffer and external device. And, the background operation comprises prefetch operation for transmitting data from cell array to row buffer and restore operation for transmitting data from row buffer to cell array. The foreground operation comprises read operation and write operation. As described above, conventional DRAMs are interfaced with external devices through row buffer. In DRAM using row buffer to accomplish compatibility with SDRAM, a control circuit is additionally required to control the row buffer since background operation and foreground operation are controlled by using /RAS, /CAS, /WE and /CS in accessing DRAM from the external.
FIG. 1
is a block diagram of conventional SDRAM. Referring to
FIG. 1
, a row active activation signal ras
6
is enabled according to active command ACT and then, a row decoder unit
40
is operated, thereby activating word line WL corresponding to row address. And, a column active activation signal casp
6
is activated according to read command and then, a column decoder unit (not shown) is operated, thereby activating bit line corresponding to column address. And, data from local data bus and global data bus are sensed and transmitted to a data output buffer
52
by a column decoder output signal Yi.
FIG. 2
is a block diagram for showing a conventional DRAM including row buffer between bit line sense amp and data bus sense amp. Referring to
FIG. 2
, an operation is additionally performed to transmit data from cell array block to row buffer.
That is, prefetch operation PFC signal is enabled, thereby selecting a register corresponding to row buffer address. And then, a signal controlling background operation of DRAM bgp
6
is activated, thereby selecting and operating one of 4 bit line sense amp BLSA connected to one transfer bus. Subsequently, data sensed in the bit line sense amp are transmitted to row buffer through transfer bus line. When a read command is received, column active activation signal casp
6
is activated and column decoder output signal Yi is outputted and then, data through local data bus LDB and global data bus GDB are sensed and outputted to data output buffer.
FIG. 3
is a block diagram for showing a state machine of conventional SDRAM. The state machine comprise clock buffer units
210
-
220
, a command decoder unit
230
, an address buffer unit
240
, an address latch unit
250
, a mode decoder unit
260
, a row address predecoder unit
270
and a column address predecoder unit
280
.
The command buffer units
210
~
216
input /RAS, /CAS, /WE and /CS, respectively and the clock buffer unit
220
inputs external clock CLK and generates internal signals clkp
2
and clkmc. The command decoder unit
230
inputs the internal command signal outputted from the command buffer units
210
~
216
and the output signal clkp
2
of the clock buffer unit
220
and outputs row active signal rasp
6
, column active signal casp
6
and internal signal mrsp
6
. The address buffer unit
240
inputs external address and the address latch unit
250
latches output signal of the address buffer unit
240
according to output signal clkmc of the clock buffer unit
220
. The mode decoder unit
260
inputs the output signal mrsp
6
of the command decoder unit
230
and output signal ea<0:10> of the address latch unit
250
and generates cas latency c
11
, c
12
and c
13
. The row address predecoder unit
270
inputs the row active signal rasp
6
and output signal ea<0:10> of the address latch unit
250
and generates a signal gax activating word line enable signal WE. The column address predecoder unit
280
inputs the column activation signal casp
6
and the output signal ea<0:10> of the address latch unit
250
and generates a signal gay activating column selection signal Yi.
According to the conventional SDRAM, /RAS, /CAS, /WE and /CS received from the external are synchronized with clock signal received from the external to generate row activation signal rasp
6
and cas activation signal casp
6
, internally. And, CAS Latency CL is determined by using address received to address buffer in the operation of mode register set MRS. However, the conventional semiconductor memory device has several problems. That is, according to the conventional SRAM, data are transmitted from DRAM core by one command (read or write). However, according to the conventional semiconductor memory device having row buffers, data are transmitted by two commands-background operation (prefetch or restore) and foreground operation (read or write). As a result, the conventional semiconductor memory device has a problem of incompatibility with SRAM.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and the object of the present invention is to provide a semiconductor memory device having row buffers being compatible with SRAM and having improved effective bandwidth by outputting cell array data according to one command.
In order to accomplish the above object, the semiconductor memory device according to the present invention comprises: a memory cell array for storing data; a row buffer for storing data of a row of the memory cell array; and a state machine for controlling the semiconductor memory device to firstly store data of the row determined by an inputted address signal from the memory cell array in the row buffer when a predetermined external command is inputted from the external, and then to output a part of the data according to the address signal from the row buffer to the external in a predetermined delay time.
The state machine comprises a command decoder for generating column activation signal, mode register set signal and first internal command signal; a mode decoder for generating mode signals determining the generation time of column activation signal according to corresponding address signal when the mode register set signal is inputted from the command decoder; and a control block for generating control signal which controls the command decoder to generate the column activation signal at the time determined by the mode signals when the first internal command signal is inputted from the command decoder according to the input

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