Semiconductor memory device having refresh circuit and word...

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S230060

Reexamination Certificate

active

07929369

ABSTRACT:
A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.

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patent: 2002/0093864 (2002-07-01), Ooishi

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