Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2011-04-19
2011-04-19
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230060
Reexamination Certificate
active
07929369
ABSTRACT:
A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.
REFERENCES:
patent: 5608682 (1997-03-01), Jinbo et al.
patent: 5715206 (1998-02-01), Lee et al.
patent: 6944081 (2005-09-01), Takahashi et al.
patent: 7170808 (2007-01-01), Hokenmaier
patent: 7177220 (2007-02-01), Chou et al.
patent: 7317650 (2008-01-01), Shinozaki et al.
patent: 7466617 (2008-12-01), Luk et al.
patent: 2002/0093864 (2002-07-01), Ooishi
Lee Dong-Hyuk
Oh Chi-Sung
Harness Dickey & Pierce
Samsung Electronics Co,. Ltd.
Tran Michael T
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