Semiconductor memory device having redundancy circuit...

Details Semiconductor memory device having redundancy circuit... Semiconductor memory device having redundancy circuit...

2000-09-07

2002-07-30

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06426902

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory devices having a redundancy circuit capable of improving redundancy efficiency.
2. Description of the Related Art
Dynamic random access memories (DRAMs) include a large number of memory cells. Unfortunately, if even one of those memory cells fails to operate properly, the entire DRAM is treated as defective. As the integration density and the processing rate of semiconductor memory devices increase, the probability that a DRAM will have at least one defective cell increases.
The yield of a wafer determines the manufacturing cost of DRAMs. The yield is represented by the ratio of the number of non-defective chips to the total number of chips manufactured on a single wafer. As the defect rate increases, the yield decreases. The ability to correct defective cells is therefore very important to improving the yield of a wafer for high integration density memory devices.
Redundancy circuits are frequently used on a chip to replace defective cells with redundant cells. A redundancy circuit corrects defective cells and improves yield. Generally, the redundancy circuit drives a redundancy memory cell block, containing a matrix of redundant rows and columns. The redundancy circuit selects a redundancy cell from the redundancy cell block to replace a defective cell of a normal memory cell block. In other words, once a row and/or column address signal addressing a defective cell is input into the redundancy circuit, the redundancy circuit selects a redundancy memory cell to replace the defective cell.
A method for replacing a defective row and/or column occurring in a normal memory cell block with a redundancy row and/or column is disclosed in U.S. Pat. No. 5,325,334. According to that patent, once a column address signal containing a defective column is input into a fuse box array, a predetermined redundancy column is activated, and the activated redundancy column replaces the entire defective column. In the fuse box array, a plurality of fuse boxes are arranged to facilitate repair of a plurality of defective columns. Each fuse box includes a plurality of fuses and is programmed by cutting/blowing one or more of the fuses to correspond to a column address signal of a defective column. Accordingly, once programmed, when a column address of a defective column is received by the programmed fuse box, a redundancy column driver gate is activated in response to the output signal of a block selection control circuit and selects the predetermined redundancy column.
A redundancy scheme according to the above U.S. Patent is illustrated schematically in FIG.
1
. As shown in
FIG. 1
, a normal memory cell block includes a plurality of banks BANK
0
-
15
. The normal memory cell block shown also includes four defective cells DEFECT_
1
-
4
. Each of the four defective cells DEFECT_
1
-
4
occurring in the normal memory cell block appears as an “x”. Redundancy cell blocks are provided at both ends of the normal memory cell block. Although each redundancy cell block may be designed to replace a plurality of defective cells, each redundancy cell block in this example is designed to replace a single defective cell.
A first defective cell DEFECT_
1
is replaced using a left redundancy cell block by programming a first fuse box FB
1
with the column address of that cell. The second, third, and fourth defective cells DEFECT_
2
, DEFECT_
3
, and DEFECT_
4
, respectively, are all caused by a defect in a bit. Each of these defective cells is replaced using a right redundancy cell block by programming a second fuse box FB
2
with the a column address of the defective bit. Using this arrangement, a column connected to a defective cell within the normal memory cell block is replaced entirely by a redundancy column. In other words, a column selection path for selecting a column containing a defective cell is blocked and redirected to a redundancy column. In this way, not only the defective cell, but also all of the normal cells within the same column, are replaced by redundancy cells in the redundancy column.
Unfortunately, however, in some cases, a redundancy column used to replace a normal column with a defective cell may also contain a defective cell. For instance, in the example shown in
FIG. 1
, even though the defective normal cell DEFECT_
1
is replaced by a non-defective redundancy cell in the redundancy column, another cell in the redundancy column is defective. Accordingly, the redundancy column cannot be used and the entire memory device is defective. The desired redundancy efficiency therefore cannot be obtained where there is a defect in the redundancy column.
Another way to improve redundancy efficiency is to increase the number of redundancy cells. Unfortunately, although increasing the number of redundancy cells increases redundancy efficiency, it also increases chip size because each additional redundancy cell takes up chip space. A redundancy circuit capable of improving redundancy efficiency with substantially invcreasing chip size is desired.
SUMMARY OF THE INVENTION
To increase the redundancy efficiency of a semiconductor memory device, a memory device according to a first embodiment of the invention includes a plurality of memory banks, wherein each of the memory banks includes a plurality of normal memory cells arranged in a matrix of rows and columns. A plurality of redundancy cells are also included, arranged in a redundancy column. The redundancy cells are used to repair normal columns containing defective normal memory cells, wherein columns in two or more memory banks are selected by a single column selection signal.
The semiconductor memory device also includes a redundancy circuit for controlling replacement of the columns containing the defective normal memory cells with the redundancy column. The redundancy circuit includes programmable decoders comprising column fuses and a plurality of bank fuses. Each of the programmable decoders can be programmed with the address of a memory bank and a column to be repaired by selectively cutting a combination of column fuses and bank fuses corresponding to the column and the bank containing the defective normal memory cell. The redundancy circuit further includes a logic circuit for ORing the output signals of the plurality of programmable decoders to generate a redundancy selection signal that enables the redundancy column.
In another embodiment of the present invention, the redundancy circuit includes a selection logic unit instead of a logic circuit. The selection logic unit generates a redundancy selection signal in response to a predetermined control signal. The redundancy selection signal enables the redundancy column that corresponds to the output signals of the plurality of programmable decoders. In this manner, the selection logic unit determines whether to generate a redundancy selection signal that enables either a redundancy column located in an area in which the redundancy circuit is positioned or a redundancy column in another area.
Using a redundancy circuit according to the present invention, defective cells having different column addresses in different banks or bank groups can be replaced with a single redundancy column. The ability to replace multiple defective cells in different columns with a single redundancy column offers improved redundancy efficiency. In addition, enabling a redundancy circuit in another area to be used to replace defective cells further improves redundancy efficiency.


REFERENCES:
patent: 4807191 (1989-02-01), Flannagan
patent: 5404331 (1995-04-01), McClure
patent: 5610865 (1997-03-01), Shin et al.
patent: 5848003 (1998-12-01), Nishikawa
patent: 5930194 (1999-07-01), Yamagata et al.

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