Semiconductor memory device having reduced chip select...

Details Semiconductor memory device having reduced chip select... Semiconductor memory device having reduced chip select...

2002-09-20

2004-03-30

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233500, C365S189011

Reexamination Certificate

active

06714463

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-59040, filed on Sep. 24, 2001, which is incorporated herein by reference in its entirety.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a reduced chip select output time (tco) from the time when an externally inputted chip select signal transitions from an inactive state to an active state, to the time when valid data is loaded on a data bus.
BACKGROUND
In general, a static random access memory (SRAM) is controlled by an external chip select signal referred to herein as /XCS. When the external chip select signal /XCS is inactive, the SRAM is in a standby mode to hold data stored therein When the external chip select signal /XCS is active, the SRAM reads/writes data from/to a memory cell, which is assigned by an address. Further, signals for pre-charging bitlines of a memory cell, or equalizing or driving a sense amplifier, are also influenced by the external chip select signal /XCS. Only in a case where a chip select signal /CS is in an enable state where a row address signal or a column address signal transitions, are bitline pre-charge signals, or a sense amplifier equalizing and driving signal, generated to perform an abnormal write/read operation.
FIG. 1
schematically illustrates an architecture of a conventional SRAM. SRAM
1
comprises a memory cell array
30
having a plurality of memory cells MCs located at intersections of rows and columns. In the memory cell array
30
, wordlines WL are provided to corresponding rows of memory cells and a pair of bitlines (BL, /BL) are provided to corresponding columns of memory cells. A target memory cell for reading and writing data is selected according to combinations of signal levels of address signals A
0
-An.
The SRAM
1
further comprises control logic
50
for controlling read/write operations of the SRAM
1
according to externally inputted signals, i.e., an external chip select signal /XCS, a write enable signal /WE, a read enable signal /RE, or other control signals (not shown). The control logic
50
generates an internal chip select signal /CS for activating an address input buffer
10
in response to the external chip select signal /XCS.
The address input buffer
10
is activated in response to the internal chip select signal /CS, receives the address signals A
0
-An from an address input terminal (not shown), and transfers internal address signals IA
0
-IAn to an address decoder
20
and the control logic
50
.
The address decoder
20
comprises a row decoder
20
and a column, decoder
22
. The row decoder
21
receives a part of address signals IA
0
-IAn from the address input buffer
10
, and activates a wordline corresponding to inputted address signals. The column decoder
22
connects a pair of bitlines corresponding to all the other address signals excluding the address signals inputted to the row decoder
21
, to a sense amplify & write driver
40
.
In response to control signals PSA and PEQ from the control logic
50
, the sense amplify & write driver
40
writes/reads data to/from a memory cell that is coupled to a bitline corresponding to address signals from the column decoder
22
.
A data input/output buffer
60
is coupled to the sense amplify & write driver
40
through a pair of data input/output lines (IO, /IO). The input/output buffer
60
transfers data between a data input/output terminal (not shown) and the sense amplify & write driver
40
. Data inputted from the data input/output terminal through a data bus, is transferred to the sense amplify & write driver
40
through the input/output buffer
60
and a pair of data input/output lines IO, /IO. Data read-out from the sense amplify & write driver
40
is outputted to the data input/output terminal through the pair of input/output lines IO and /IO, the data input/output buffer
60
, and the data bus
70
.
The control logic
50
receives the address signals IA
0
-IAn from the address input buffer
10
, and outputs pulse signals PWL, PSA, PEQ, and MMX, which are needed to perform a write/read operation when the address signals IA
0
-IAn transition. For example, the pulse signal PWL is a signal for enabling the row decoder
21
, the pulse signal PSA is a signal for driving the sense amplify & write driver
40
, the pulse signal PEQ is a signal for equalizing the sense amplify & write driver
40
, and the pulse signal PMX is a signal for driving the data input/output buffer
60
.
FIG. 2
illustrates an architecture of the control logic
50
of the SRAM
1
shown in FIG.
1
. The control logic
50
comprises a chip select buffer
51
, a short pulse generation circuit
52
, an address transition detect (ATD) circuit
53
, and a pulse generation circuit
54
. The chip select buffer
51
generates an internal chip select signal /CS for activating the address buffer
10
, and a control signal /CSATD for activating the address transition detect circuit
53
in response to an external chip select signal /XCS. The short pulse generation circuit
52
receives the address signals IA
0
-IAn from the address input buffer
10
to generate short pulse signals SP
0
-SPn when the address signals IA
0
-IAn transition. The address transition detect circuit
53
summates the short pulse signals SP
0
-SPn from the short pulse generation circuit
52
to generate an address transition detect signal ATD in response to the control signal /CSATD. The pulse generation circuit
54
generates a series of pulse signals PWL, PSA, PEQ, and PMX, which are needed to start a write/read operation in response to the address transition detect signal ATD.
FIG. 3
illustrates an architecture of the chip select buffer
51
. The chip select buffer
51
comprises a NOR gate
101
, inverters
102
-
104
, a delay unit
105
, and a NAND gate
106
.
The NOR gate
101
has input terminals and an output terminal. The input terminals receive the external chip select signal /XCS and a signal of a ground voltage level (i.e., logic “0”). The inverters
102
-
104
are sequentially coupled between the output terminal of the NOR gate and a chip select output terminal /CS in cascade. Therefore, when the external chip select signal /XCS transitions from high to low, the internal chip select signal /CS becomes active at a high level.
The delay unit
105
delays an output signal from the output terminal of the NOR gate
101
by a predetermined time. The NAND gate
106
has input terminals and an output terminal. The input terminals of the NAND gate
106
receive an output signal from the output terminal of the NOR gate
101
and a signal delayed by the delay unit
105
. The output terminal of the NAND gate
106
outputs a control signal /CSATD for controlling the address transition detect circuit
53
. Thus, if the external chip select signal /XCS is maintained in low level for a longer time than a delay time of the delay unit
105
, the control signal /CSATD becomes active at the high level.
FIG. 4
illustrates architectures of the address input buffer
10
and the short pulse generation circuit
52
. The address input buffer
10
comprises NOR gates
110
-
112
each corresponding to their externally inputted address signals A
0
-An. Each of the NOR gates
110
-
112
receives the internal chip select signal /CS and a corresponding address signal to carry out a NOR operation.
FIG. 5
illustrates an architecture of the address transition detect circuit
53
shown in FIG.
2
. The address transition detect circuit
53
comprises a PMOS transistor
131
, inverters
132
,
134
, and
138
, a latch
140
, a NOR gate
133
, an NMOS transistor
137
, and N of NMOS transistors
150
-
152
. The PMOS transistor
131
has a current path formed between a power supply voltage and a first node N
1
with a control gate. The latch
140
comprises inverters
135
and
136
, and has one end coupled to the first node and the other end. The inverter
134
has an input terminal coupled to the other end of t

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