Semiconductor memory device having power decoupling capacitor

Details Semiconductor memory device having power decoupling capacitor Semiconductor memory device having power decoupling capacitor

2006-02-24

2008-12-09

Purvis, Sue A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S534000, C257SE29309, C257SE21679, C257SE21423, C257SE21210, C257SE21180

Reexamination Certificate

active

07462912

ABSTRACT:
Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.

REFERENCES:
patent: 6433381 (2002-08-01), Mizutani et al.
patent: 6803641 (2004-10-01), Papa Rao et al.
patent: 7166882 (2007-01-01), Nakamura et al.
patent: 2006/0113633 (2006-06-01), Park et al.
patent: 1998-035297 (1998-08-01), None
patent: 2000-0045346 (2000-07-01), None
patent: 2000-0066946 (2000-11-01), None
English language abstract of Korean Publication No. 1998-035297.
English language abstract of Korean Publication No. 2000-0045346.
English language abstract of Japanese Publication No. 2000-0066946.

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