Semiconductor memory device having low power self refresh and bu

Details Semiconductor memory device having low power self refresh and bu Semiconductor memory device having low power self refresh and bu

1996-08-30

1997-08-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

36523006, 365236, 365239, G11C 700

Patent

active

056549300

ABSTRACT:
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

REFERENCES:
patent: 5130923 (1992-07-01), Warriner et al.
patent: 5146430 (1992-09-01), Torimaru et al.
patent: 5283764 (1994-02-01), Kim et al.
patent: 5361237 (1994-11-01), Chishiki
patent: 5365487 (1994-11-01), Patel et al.

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