Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
2005-07-20
2010-12-21
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S196000, C365S203000, C365S205000, C365S207000, C365S208000
Reexamination Certificate
active
07855926
ABSTRACT:
A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
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English language abstract of the Korean Publication No. 2001-84782.
Changsik Yoo, et al., “A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration” IEEE Journal of solid-state circuits, vol. 39, No. 6, Jun. 2004. pp. 941-951.
Jun Young-Hyun
Kim Chul-Soo
Lee Sang-Bo
Shin Sang-Woong
Muir Patent Consulting, PLLC
Phan Trong
Samsung Electronics Co,. Ltd.
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