Semiconductor memory device having IO line pair to be equalized

Details Semiconductor memory device having IO line pair to be equalized Semiconductor memory device having IO line pair to be equalized

1992-08-21

1994-07-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36523003, 3652335, G11C 700

Patent

active

053315952

ABSTRACT:
In DRAM divided into plurality of blocks and operating on a block basis, each equalizing circuit is controlled such that release of equalization of an IO line pair is carried out only in a block having a memory cell from which data is to be read for data reading. Since a MOS transistor 40 provided between two IO lines constituting each IO line pair 2 for equalization of these lines and its release is not switched from on to off wastefully, current consumed for charge/discharge of a gate of the MOS transistor is considerably reduced compared to a conventional case.

REFERENCES:
patent: 4926384 (1990-05-01), Roy
patent: 4977373 (1990-11-01), Kim
patent: 5214610 (1993-05-01), Houston

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