Semiconductor memory device having improved redundancy scheme

Details Semiconductor memory device having improved redundancy scheme Semiconductor memory device having improved redundancy scheme

2005-03-22

2005-03-22

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S051000

Reexamination Certificate

active

06870780

ABSTRACT:
A semiconductor memory device with an improved redundancy scheme is provided. The semiconductor memory device includes at least one memory block having a plurality of memory banks that are arranged in a column direction. Each memory bank includes a plurality of normal memory cells, which are arranged according to a row and column structure, and at least one redundancy memory cell to replace defective memory cells. At least one memory bank, adjacent to an edge of photo shot or an edge of chip, among the plurality of memory banks includes more redundancy lines than the other memory banks. In the semiconductor memory device, when memory banks have different numbers of defective memory cells to be repaired, the number of redundancy memory cells of each memory bank is differently set, thus increasing the yield.

REFERENCES:
patent: 5831914 (1998-11-01), Kirihata
patent: 6343306 (2002-01-01), Lo
patent: 1999-001473 (1999-01-01), None
patent: 01-69203 (2001-07-01), None

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