Semiconductor memory device having high speed parallel transmiss

Details Semiconductor memory device having high speed parallel transmiss Semiconductor memory device having high speed parallel transmiss

1996-04-26

1997-09-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365198, G11C 700

Patent

active

056639139

ABSTRACT:
A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

REFERENCES:
patent: 3453607 (1969-07-01), Cohler et al.
patent: 3585399 (1971-06-01), Andrews, Jr.
patent: 5239215 (1993-08-01), Yamaguchi
patent: 5304969 (1994-04-01), Jacobowitz et al.

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