Semiconductor memory device having hierarchical bit line structu

Details Semiconductor memory device having hierarchical bit line structu Semiconductor memory device having hierarchical bit line structu

1995-08-18

1997-07-29

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Precharge

365205, 365207, 365204, 365 63, 365190, 36523003, G11C 502, G11C 1124

Patent

active

056527268

ABSTRACT:
A semiconductor memory device comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits. The subbit line pairs are provided in correspondence to the main bit line pair. One and other subbit lines of the subbit line pairs are arranged in straight lines along the main bit line pair. The selection transistors are provided in correspondence to the subbit line pairs. Each of the selection transistor pairs is connected between the main bit line pair and the corresponding subbit line pair, and turned on in response to a prescribed selection signal. The word lines are arranged to intersect with one and the other subbit lines of the subbit line pairs. The memory cells are provided in correspondence to intersection points between one and the other subbit lines of the subbit line pairs and the word lines. Each of the memory cells is connected to the corresponding subbit line and the corresponding word line. The first precharging circuits are provided in correspondence to the subbit line pairs. Each of the first precharging circuits directly precharges the corresponding subbit line pair at the prescribed precharging potential.

REFERENCES:
patent: 5291432 (1994-03-01), Furutani
patent: 5291450 (1994-03-01), Fujwara et al.
patent: 5436870 (1995-07-01), Sato et al.
patent: 5495440 (1996-02-01), Asakura et al.
NAND-Structured Cell Technologies for 256Mb DRAMs, T Yamada et al, Technical Repot of IEICE, SDM94-18, ICD94-29 (1994-05) vol. 94, No. 72, pp. 13-18.
NAND-Structured Cell Technologies for Low Cost 256Mb DRAMs, T. Hamamoto et al, IEDM 93 Technical Digest, pp. 643-646.

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