Semiconductor memory device having hierarchical bit line...

Details Semiconductor memory device having hierarchical bit line... Semiconductor memory device having hierarchical bit line...

2007-01-02

2007-01-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189011, C365S185140

Reexamination Certificate

active

10997919

ABSTRACT:
A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; a precharge circuit including an output terminal being connected to the pair of local bit lines; a local write amplifier circuit including a data input terminal being connected to the pair of global bit lines and an output terminal being connected to the pair of local bit lines; and a control signal line being connected to an input terminal of the precharge circuit and to a control input terminal of the local write amplifier circuit, wherein the local write amplifier circuit is deactivated by the control signal line when the precharge circuit is activated, and the precharge circuit is deactivated by the control signal line when the local write amplifier circuit is activated.

REFERENCES:
patent: 6091629 (2000-07-01), Osada et al.
patent: 6542424 (2003-04-01), Endo et al.
Cangsang Zhao et al., An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/s/pin, IEEE International Solid-State Circuits Conference Digest of Technical Papers, Session 11, Paper TA 11.6, Feb. 16, 1999, pp. 200, 201 and 461.

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