Semiconductor memory device having global bit line precharge...

Details Semiconductor memory device having global bit line precharge... Semiconductor memory device having global bit line precharge...

2000-06-27

2001-08-14

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230030, C365S189050, C365S189060, C365S189110, C365S190000, C365S051000, C365S194000

Reexamination Certificate

active

06275430

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having two or more precharge circuits, which is capable of providing a high speed of operation and a stable read/write operation.
DESCRIPTION OF THE PRIOR ART
A semiconductor memory device includes a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM), such as a single data rate (SDR) SDRAM and a double data rate (DDR) SDRAM.
In a read operation, a semiconductor memory device reads out data from a selected memory cell and transfers it via a global I/O (input/output) line pairs to an external circuit. In a write operation, the semiconductor memory device writes data to a selected memory cell via the global I/O line pairs. The global I/O line pair includes a global I/O line and a complementary, or inverted, global I/O line. The global I/O line pair transmit data signals, which are complementary to each other.
The semiconductor memory device has three operational modes in transmitting data via the global I/O line pair. In a standby mode, i.e., before starting the read or write operation, the global I/O line pair is in a state of a power supply voltage level. In a data transfer mode, one of the global I/O line pair, e.g., a global I/O line, becomes a low level when data is applied to the global I/O line pair. In a precharge mode, the global I/O line is precharged to the power supply voltage level in order to prepare a next read or write operation.
FIG. 1
is a block diagram showing a semiconductor memory device having a conventional precharge structure.
As shown in
FIG. 1
, a conventional semiconductor memory device includes a global I/O line pair having a global I/O line GIO and a complementary global I/O line /GIO, a plurality of banks
100
and
101
coupled to the global I/O line pair, a data I/O buffer
113
for inputting an input data from an external circuit and outputting an output data to the external circuit and a precharge circuit
112
for precharging the global I/O line pair to a power supply voltage level.
In a bank A
100
as one of the banks, a plurality of memory cell arrays
102
and
103
containing memory cells stores data. A write driver
106
receives data from the global I/O line pair via a local I/O line pair LIO and /LIO, to write the data to a selected memory cell. A sense amplifier
107
senses and outputs data stored in a selected memory cell. The other banks, e.g., a bank B
101
, have the same structure as the bank A
100
.
At this time, a data signal at the global I/O line is delayed due to a plurality of RC loads
110
and
111
, which are composed of resistance components and capacitance components distributed on the global I/O line pair. The delay of the data signal is generally proportional to a length of the global I/O line pair.
As shown in
FIG. 1
, the bank A
100
is located far from the data I/O buffer
113
and the bank B
101
is located closely to the data I/O buffer
113
. A reference symbol N
A
represents a node of the global I/O line pair to which the bank A
100
is coupled, and a reference symbol N
B
represents a node of the global I/O line pair to which the bank B
101
is coupled.
FIG. 2
is a circuit diagram showing a precharge circuit shown in FIG.
1
.
Referring to
FIG. 2
, the precharge circuit
112
includes a pull-up driving portion
210
coupled to the global I/O line pair, a clamping portion
230
coupled to the global I/O line pair and a precharging portion
250
.
In a transfer mode, for example, when a voltage level of a global I/O line GIO becomes low, the pull-up driving portion
210
pulls up a voltage level of the complementary global I/O line /GIO in response to the low voltage level of the global I/O line GIO. The pull-up driving portion
210
includes two PMOS transistors PM
201
and PM
202
, coupled between a power supply voltage source (Vcc) and the global I/O line pair, respectively, each of whose gates is cross coupled to the global I/O line pair.
The clamping portion
230
maintains a voltage level of the global I/O line pair at a power supply voltage level before starting the read or write operation. The clamping portion
230
includes a PMOS transistor PM
203
coupled between a power supply voltage level and the global I/O line GIO, whose gate is coupled to a ground, and a PMOS transistor PM
204
coupled to the complementary global I/O line /GIO, whose gate is coupled to the ground.
The precharging portion
250
senses a level transition to the low voltage level of the global I/O line pair, and then precharges the global I/O line pair to the power supply voltage level after a predetermined time.
In the precharging portion
250
, a precharge enable signal generating unit
255
detects a voltage difference between the global I/O line and the complementary global I/O line to generate a precharge enable signal GIO_PCG. A GIO precharge unit
256
precharges the global I/O line GIO in response to the precharge enable signal GIO_PCG, and a /GIO precharge unit
257
precharges the complementary I/O line /GIO in response to the precharge enable signal GIO_PCG.
The precharge enable signal generating unit
255
includes a NAND gate ND
201
for NANDing the signal of the global I/O line GIO and the signal of the complementary global I/O line /GIO, an inverter INV
201
for inverting an output of the NAND gate ND
201
and a delay unit
253
for delaying an output of the inverter INV
201
for a predetermined time. An output signal from the delay unit
253
corresponds to the precharge enable signal GIO_PCG.
The GIO precharge unit
256
is implemented with a PMOS transistor PM
205
coupled between the power supply voltage source and the global I/O line GIO, whose gate receives the precharge enable signal GIO_PCG. The /GIO precharge portion
257
is also implemented with a PMOS transistor PM
206
coupled between the power supply voltage source and the complementary global I/O line /GIO, whose gate receives the precharge enable signal GIO_PCG.
The PMOS transistors PM
205
and PM
206
are turned on in response to the precharge enable signal GIO_PCG of a low level, so that the global I/O line GIO and the complementary global I/O line /GIO are precharged to the power supply voltage level.
FIG. 3
is a timing chart showing a level transition of a global I/O line pair in a read operation with respect to the bank A shown in FIG.
1
.
Referring to
FIG. 3
, in a read operation, one memory cell contained in a memory cell array of the bank A
100
is selected. The sense amplifier
107
senses and amplifies data stored in the selected memory cell to output an amplified data to the node N
A
of the global I/O line pair via the local I/O line pair. Then, the amplified data is transferred to the data I/O buffer
113
from the node N
A
through the node N
B
. The data I/O buffer
113
outputs the amplified data to the external circuit.
As shown, when the data is transferred via the global I/O line pair, the precharge circuit
112
senses the level transition of the global I/O line pair to the low voltage level, and generates the precharge enable signal GIO_PCG after a predetermined time, thereby precharging the global I/O line pair to the power supply voltage level.
At this time, a waveform at the node N
A
has a steep precharge slope. However, a waveform at the node N
B
has a smooth precharge slope due to the RC loads
110
and
111
distributed on the global I/O line pair.
FIG. 4
is a timing chart showing a level transition of a global I/O line pair in a write operation with respect to the bank A shown in FIG.
1
.
Referring to
FIG. 4
, in a write operation, the data I/O buffer
113
receives a data from an external circuit and transmits the data to the global I/O line pair. The data is transferred from the node N
B
to the node N
A
, and then, the write driver
106
writes the data to a selected memory cell contained in a memory cell array of the bank A
100
.
At this time, a waveform at the node N
B
has a steep precharge slope. However, a waveform

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