Semiconductor memory device having floating gate transistors

Details Semiconductor memory device having floating gate transistors Semiconductor memory device having floating gate transistors

1998-06-18

2000-02-29

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700

Patent

active

060317728

ABSTRACT:
A semiconductor memory device of the present invention comprises a memory cell array including row lines, column lines and memory cells arranged in rows and columns is disclosed. Each memory cell is connected to one of the row lines and one of the column lines. The semiconductor memory device further comprises a row select circuit connected to the row lines for selecting one of the row lines in response to a row select signal, a column select circuit connected to the column lines for selecting one of the column lines in response to a column select signal, a potential detector connected to the memory cell array for detecting a potential level of the lines of the memory cell array, and a test memory cell array connected to said potential detector through a test line. The test memory cell array tests a structural default of the row lines. The test memory cell array has a row of transistors each of which has a source connected to a potential source. The drains of the transistors are connected to the test line and to nothing in turn.

REFERENCES:
patent: 5590075 (1996-12-01), Mazzali
patent: 5606527 (1997-02-01), Kwack et al.
patent: 5646891 (1997-07-01), Okamoto
patent: 5742615 (1998-04-01), Kondo et al.
patent: 5867436 (1999-02-01), Furutani et al.
patent: 5870333 (1999-02-01), Matsumoto

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