Semiconductor memory device having fast writing circuit for test

Details Semiconductor memory device having fast writing circuit for test Semiconductor memory device having fast writing circuit for test

1996-06-24

1998-03-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518904, G11C 1300

Patent

active

057269394

ABSTRACT:
The time required for testing high-density semiconductor memory devices is reduced by circuits and methodology for rapidly writing test data bits into the memory array. A common word line enable signal is arranged to turn on all of the word lines in the array simultaneously. Test data bits are applied to the array by gating them onto the I/O lines so that separate test bit lines are not required. A fast test enable signal gates the test bits onto the I/O lines in all columns of the array simultaneously, so that all of the memory cells receive test bits at one time. The new circuitry has the further advantages of reduced area and capacitance, the latter further contributing to reducing the test data write time.

REFERENCES:
patent: 5140553 (1992-08-01), Choi et al.
patent: 5208778 (1993-05-01), Kumanoya et al.
patent: 5253211 (1993-10-01), Suzuki
patent: 5276648 (1994-01-01), Yanagisawa et al.

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