Semiconductor memory device having equalization signal generatin

Details Semiconductor memory device having equalization signal generatin Semiconductor memory device having equalization signal generatin

1994-09-14

1996-01-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365207, 365194, 36523003, 365233, G11C 700

Patent

active

054870437

ABSTRACT:
The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines. Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.

REFERENCES:
patent: 5285416 (1994-02-01), Tokami et al.
patent: 5404338 (1995-04-01), Murai et al.
"A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines", by Masataka Matsui et al, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 733-740.

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