Semiconductor memory device having divided word line

Details Semiconductor memory device having divided word line Semiconductor memory device having divided word line

1997-10-01

1998-08-18

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 365203, G11C 700

Patent

active

057966648

ABSTRACT:
In a DRAM having a plurality of memory array blocks, each of which has a plurality of sub-word lines connected to a main word line, a cell plate is provided correspondingly to each memory array block. A fuse is interposed between a cell plate potential supply line supplying a cell plate potential to the cell plate in each memory array block and the cell plate. By blowout of the fuse, supply of the cell plate potential to defective one among the memory array blocks is cut off. Thereby, a current consumption during standby is suppressed.

REFERENCES:
patent: 5193074 (1993-03-01), Anami
patent: 5487041 (1996-01-01), Wada
patent: 5519657 (1996-05-01), Arimoto
patent: 5574729 (1996-11-01), Kinoshita et al.
Goro Kitsukawa et al, "256Mb DRAM Technologies for File Applications", 1993 IEEE International Solid-State circuits Conference, pp. 48-49.
Masahiko Yoshimoto et al, "A 64Kb Full CMOS RAM with Divided Word Line Structure", 1983 IEEE International Solid-State Circuits Conference, pp. 58-59.

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