Static information storage and retrieval – Read/write circuit – Testing
Patent
1996-11-25
1998-08-11
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
36523003, G11C 700
Patent
active
057936862
ABSTRACT:
Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.
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patent: 5305267 (1994-04-01), Haraguchi
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patent: 5400281 (1995-03-01), Morigami
patent: 5444661 (1995-08-01), Matsui
patent: 5615166 (1997-03-01), Machida
Mori et al."A 45ns 64Mb DRAM with a Merged Match-line Test Architecture" 1991 IEEE International Solid-State Circuits Conference, pp. 110-111.
Asakura Mikio
Furutani Kiyohiro
Hamade Kei
Hidaka Hideto
Nakaoka Yoshito
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
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