Semiconductor memory device having data input/output circuit of

Details Semiconductor memory device having data input/output circuit of Semiconductor memory device having data input/output circuit of

1998-05-13

1999-09-14

Mai, Son

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 326 83, G11C 700

Patent

active

059532610

ABSTRACT:
Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

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Mori et al., A 45ns 64Mb DRAM with a Merged Match-line Test Architecture 1991, IEEE International Solid-State Circuits Conference, pp. 110-111.

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