Semiconductor memory device having data bus reset circuit

Details Semiconductor memory device having data bus reset circuit Semiconductor memory device having data bus reset circuit

1987-09-16

1989-04-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365202, G11C 1300, G11C 1140

Patent

active

048212326

ABSTRACT:
A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

REFERENCES:
patent: 4578776 (1986-03-01), Takemae
patent: 4584670 (1986-04-01), Michael
patent: 4589096 (1986-05-01), Kaneko
patent: 4601017 (1986-07-01), Mochizuki

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