Semiconductor memory device having controllable redundant scheme

Details Semiconductor memory device having controllable redundant scheme Semiconductor memory device having controllable redundant scheme

1987-02-09

1989-02-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365200, G11C 700

Patent

active

048092282

ABSTRACT:
A semiconductor memory device having a controllable majority decision reading scheme is disclosed. The memory is featured in that a number of memory cells to be selected in one access cycle is varied by at least one control signal and a logic state of a read-out signal is determined by data derived from the desired number of memory cell on cells.

REFERENCES:
patent: 4675849 (1987-06-01), Kinoshita

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